CDCM1802RGTT datasheet(7/22 Pages) TI

7 / 22 page

CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

jitter characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Additive phase jitter from input to

LVPECL output Y0

12 kHz to 20 MHz, fout = 250 MHz to 800 MHz,

divide by 1 mode

0.15

ps rms

tjitterLVPECL

LVPECL output Y0,

See Figure 2

50 kHz to 40 MHz, fout = 250 MHz to 800 MHz,

divide by 1 mode

0.25

ps rms

Additive phase jitter from input to

LVCMOS output Y1

12 kHz to 20 MHz, fout = 250 MHz,

divide by 1 mode

0.25 ps rms

tjitterLVCMOS

LVCMOS output Y1,

See Figure 3

50 kHz to 40 MHz, fout = 250 MHz,

divide by 1 mode

0.4

ps rms

Figure 2

−160

−155

−150

−145

−140

−135

−130

−125

−120

−115

−110

VDD = 3.3 V

TA = 25°C

f = 622 MHz

÷1 Mode

ADDITIVE PHASE NOISE

FREQUENCY OFFSET FROM CARRIER − LVPECL

f − Frequency Offset From Carrier − Hz

100

100M

10k

100k

10M

Figure 3

−160

−155

−150

−145

−140

−135

−130

−125

−120

−115

−110

−105

−100

VDD = 3.3 V

TA = 25°C

f = 250 MHz

÷1 Mode

ADDITIVE PHASE NOISE

FREQUENCY OFFSET FROM CARRIER − LVCMOS

f − Frequency Offset From Carrier − Hz

100

100M

10k

100k

10M

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