DS26334 datasheet(13/115 Pages) DALLAS

13 / 115 page

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

13 of 115

NAME

TYPE

FUNCTION

RCLK1

RCLK2

RCLK3

RCLK4

RCLK5

RCLK6

RCLK7

P10

RCLK8

P13

RCLK9

L13

RCLK10

K14

RCLK11

G13

RCLK12

F12

RCLK13

RCLK14

RCLK15

RCLK16

tri-state

Receive Clock for Channels 1–16. The receive data (RPOS/RNEG)

is clocked out on the rising edge of RCLK. If a given receiver is in

power-down mode the RCLK is high impedance. Upon a LOS being

detected, the RCLK is switched from the recovered clock to MCLK.

RCLK can be inverted by the RCLKI register.

MCLK

H12

Master Clock. This is an independent free-running clock that can be

a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz ±50ppm

for T1 mode. The clock selection is available by MC bits MPS0,

MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be internal

adapted to 1.544MHz and a multiple of 1.544MHz can be internal

adapted to 2.048MHz.

LOS1

LOS2

LOS3

LOS4

LOS5

LOS6

LOS7

LOS8

LOS9

R14

LOS10

N15

LOS11

K15

LOS12

H15

LOS13

B10

LOS14

LOS15/TECLK

E11

LOS16/CLKA

F10

Loss-of-Signal Output. This output goes high when there is no

transition on the received signal over a specified interval. The output

will go low when there is sufficient ones density in the received signal.

The LOS criteria for assertion and desertion criteria are described in

Section 5.5.5. The LOS outputs can be configured to comply with

T1.231, ITU G.775 or ETSI 300 233.

T1/E1 Clock (TECLK) (Ball E11 only). This output becomes a T1 or

E1 programmable clock output when enabled by register MC. For T1

or E1 frequency selection see register CCR.

Clock A (CLKA) (Ball F10 only). This output becomes a

programmable clock output when enabled by register MC. For

frequency options see register CCR.

HOST SELECTION

MODESEL

Mode Selection. This pin is used to select the control mode of the

DS26334:

Low

® serial host mode

High

® parallel host mode

MOTEL

Motorola Intel Select. When this pin is low, Motorola mode is

selected. When this pin is high Intel mode is selected.

CSB

P14

Chip Select Bar. This signal must be low during all accesses to the

registers.

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