ADAU1761BCPZ-R7 datasheet(61/93 Pages) AD

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Data Sheet

ADAU1761

Rev. D | Page 61 of 93

R11: ALC Control 0, 16,401 (0x4011)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PGASLEW[1:0]

ALCMAX[2:0]

ALCSEL[2:0]

Table 45. ALC Control 0 Register

Bits

Bit Name

Description

[7:6]

PGASLEW[1:0]

PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease

takes to ramp up or ramp down to the target volume set in Register R8 (left differential input volume control)

and Register R9 (right differential input volume control).

Setting

Slew Time

24 ms (default)

48 ms

96 ms

Off

[5:3]

ALCMAX[2:0]

The maximum ALC gain sets a limit to the amount of gain that the ALC can provide to the input signal. This

protects small signals from excessive amplification.

Setting

Maximum ALC Gain

000

−12 dB (default)

001

−6 dB

010

0 dB

011

6 dB

100

12 dB

101

18 dB

110

24 dB

111

30 dB

[2:0]

ALCSEL[2:0]

ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds

only to the right channel input and controls the gain of the right PGA amplifier only. When set to left only, the

ALC responds only to the left channel input and controls the gain of the left PGA amplifier only. When set to

stereo, the ALC responds to the greater of the left or right channel and controls the gain of both the left and

right PGA amplifiers. DSP control allows the PGA gain to be set within the DSP or from external GPIO inputs.

These bits must be off if manual control of the volume is desired.

Setting

Channels

000

Off (default)

001

Right only

010

Left only

011

Stereo

100

DSP control

101

Reserved

110

Reserved

111

Reserved

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