PEX 8747, PCI Express Gen 3 Switch, 48 Lanes, 5 Ports

Highlights

PEX 8747 General Features

o

48-lane, 5-port PCIe Gen 3 switch

-

Integrate 8.0 GT/s SerDes

d

27 x 27mm

o

o

Typical Power: 8.0 Watts

res

PEX 8747 Key Featu

o

a

St ndards Compliant

-

PCI Express Base Specification, r3.0

)

(compatible w/ PCIe r1.0a/1.1 & 2.0

ec, r1.2

-

PCI Power Management Sp

-

Microsoft Vista Compliant

ices

-

Supports Access Control Serv

-

Dynamic link-width control

peed control

-

Dynamic SerDes s

o

gh

Hi

Performance

♦

performancePAK

ng (bandwidth throttling)

Read Paci

Multicast

t Pool

Dynamic Buffer/FC Credi

ic

-

Non-blocking switch fabr

-

Full line rate on all ports

-

Packet Cut-Thru with 100ns max packet

latency (x16 to x16)

-

2KB Max Payload Size

o

Flexible Configuration

-

Ports configurable as x8 or x16

-

Registers configurable with strapping

2

t software

pins, EEPROM, I C, or hos

-

Lane and polarity reversal

0a PM

-

Compatible with PCIe 1.

o

Quality of Service (QoS)

-

Eight traffic classes per port

-

Weighted round-robin source

port arbitration

o

ailability, Serviceability

Reliability, Av

♦ visionPAK

Per Port Performance Monitoring

header counters

Per port payload &

SerDes Eye Capture

PCIe Packet Generator

Error Injection and Loopback

-

All ports hot plug capable thru I

port)

(Hot Plug Controller on every

bit support

-

ECRC and Poison

-

Data Path parity

-

Memory (RAM) Error Correction

ignals

-

INTA# and FATAL_ERR# s

-

Advanced Error Reporting

-

ailable

Port Status bits and GPIO av

• Per port error diagnostics

-

JTAG AC/DC boundary scan

The ExpressLane™ PEX 8747 device offers Multi-Host PCI Express

switching capability enabling users to connect a host to its respective

endpoints via scalable, high bandwidth, non-blocking interconnection

to a variety of graphics applications. The PEX 8747 is optimized to

support high-resolution graphics while supporting peer-to-peer traffic

and multicast for maximum performance.

High Performance & Low Packet Latency

The PEX 8747 architecture supports packet cut-thru with a maximum

latency of 100ns (x16 to x16). This, combined with large packet memory,

flexible common buffer/FC credit pool and non-blocking internal switch

architecture, provides full line rate on all ports for performance-hungry

applications such as servers and switch fabrics. The low latency enables

applications to achieve high throughput and performance. In addition to low

latency, the device supports a packet payload size of up to 2048 bytes,

enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8747 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction circuitry

throughout the internal data paths as packets pass through the switch.

Flexible Configuration

The PEX 8747’s 5 ports can be

configured to lane widths of x8 or

x16. Flexible buffer allocation,

along with the device's flexible

packet flow control, maximizes

throughput for applications where

more

traffic

flows

in

the

downstream,

rather

than

upstream, direction. Any port can

be designated as the upstream

port,

which

can

be

changed

dynamically.

Figure

1

shows

some of the PEX 8747’s common

port configurations.

Figure 1. Common Port Configurations

PEX 8747

x16

PEX 8747

x16

x16

x16

x16 x8 x8

PEX 8747

x16

x8 x8 x8 x8

SerDes Power and Signal Management

The PEX 8747 provides low power capability that is fully compliant with the

PCIe power management specification and supports software control of the

SerDes outputs to allow optimization of power and signal strength in a

system. Furthermore, the SerDes block supports loop-back modes and

advanced reporting of error conditions, which enables efficient

management of the entire system.

© PLX Technology, www.plxtech.com

Page 1 of 4

10/20/2010, Version 1.0