PEX8764, PCI Express Gen3 Switch, 64 Lanes, 16 Ports

© PLX Technology, www.plxtech.com

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07Oct13; v1.3

SSC Isolation

The PEX8764 employs a multi-clock domain which

allows the user to terminate Spread Spectrum Clock

enabled domains. Terminating the SSC clock removes

the need to pass a common clock across a backplane.

The PEX8764 supports SSC isolation on all of its ports.

visionPAK

TM

Another PLX exclusive, visionPAK is a debug

diagnostics suite of integrated hardware and software

instruments that users can use to help bring their systems

to market faster. visionPAK features consist of

Performance Monitoring, SerDes Eye Capture, Error

Injection, SerDes Loopback, and more.

Performance Monitoring

The PEX8764’s real time performance monitoring

allows users to literally “see” ingress and egress

performance on each port as traffic passes through the

switch using PLX’s Software Development Kit (SDK).

The monitoring is completely passive and therefore has

no affect on overall system performance. Internal

counters provide extensive granularity down to traffic &

packet type and even allows for the filtering of traffic

(i.e. count only Memory Writes).

SerDes Eye Capture

Users can evaluate their system’s signal integrity at the

physical layer using the PEX8764’s SerDes Eye Capture

feature. Using PLX’s SDK, users can view the receiver

eye of any lane on the switch. Users can then modify

SerDes settings and see the impact on the receiver eye.

Figure 5 shows a screenshot of the SerDes Eye Capture

feature in the SDK.

Figure 5. SerDes Eye Capture

Error Injection & SerDes Loopback

Using the PEX8764’s Error Injection feature, users can

inject malformed packets and/or fatal errors into their

system and evaluate a system’s ability to detect and

recover from such errors. The PEX8764 also supports

Internal Tx, External Tx, Recovered Clock, and

Recovered Data Loopback modes.

Applications

Suitable for host-centric as well as peer-to-peer traffic

patterns,

the PEX8764 can be configured for a wide

variety of form factors and applications.

Host Centric Fan-out

The PEX8764, with its symmetric or asymmetric lane

configuration capability, allows user-specific tuning to a

variety of host-centric applications. Figure 6 shows a

server

design where, in a quad or multi processor

system, users can assign endpoints/slots to CPU cores to

distribute the system load. The packets directed to

different CPUs will go to different (user assigned)

PEX8764 upstream ports, allowing better queuing and

load balancing capability for higher performance.

Figure 6. Host Centric Dual Upstream