AD9544SLASHPCBZ datasheet(58/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 58 of 62

DATA BIT N – 1

DATA BIT N

CSB

SCLK

SDIO

SDO

tDV

Figure 56. Timing Diagram for Serial Control Port Register Read—MSB First

CSB

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1

A9 A10 A11 A12

R/W

A14

A13

D5 D6

Figure 57. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 58. Serial Control Port Timing—Write

Table 36. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and the rising edge of SCLK

tDH

Hold time between data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between the CSB falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CSB rising edge (end of the communication cycle)

tHIGH

Minimum period that SCLK is in a logic high state

tLOW

Minimum period that SCLK is in a logic low state

tDV

SCLK to valid SDIO (see Figure 56)

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