ADF4155 datasheet(3/32 Pages) AD

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Data Sheet

ADF4155

SPECIFICATIONS

AVDD = DVDD = RFVDD = 3.3 V ± 5%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = RFGND = CPGND = 0 V, and TA = TMIN to TMAX, unless otherwise

noted. Operating temperature range is −40°C to +85°C.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFIN+\REFIN− CHARACTERISTICS

Input Frequency

For f < 10 MHz, ensure slew rate > 21 V/µs

Single-Ended Mode

250

MHz

Differential Mode

600

MHz

Input Sensitivity

Single-Ended Mode

0.7

AVDD

V p-p

REFIN+ biased at AVDD/2; ac coupling ensures

AVDD/2 bias

Differential Mode

0.4

1.8

V p-p

LVDS and LVPECL compatible, REFIN+\REFIN−

biased at 2.1 V; ac coupling ensures 2.1 V bias

Input Capacitance

Single-Ended Mode

6.9

Differential Mode

1.4

Input Current

±60

µA

PHASE DETECTOR

Phase Detector Frequency

125

MHz

Negative bleed on

100

MHz

Pulsed bleed on

125

MHz

Negative bleed off and pulsed bleed off

MHz

CSR enabled

RFIN+\RFIN− CHARACTERISTICS

For lower frequencies, ensure that the slew

rate > 400 V/µs

RF Input Frequency

0.5

6.0

GHz

−10 dBm minimum/0 dBm maximum

8.0

GHz

−5 dBm minimum/0 dBm maximum

Prescaler Output Frequency

1.5

GHz

CHARGE PUMP (CP)

ICP Sink/Source

RSET = 4.7 kΩ

High Value

Low Value

0.31

RSET Range

2.7

4.7

kΩ

Sink and Source Current Matching

0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP

0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature

1.5

VCP = 2.5 V

LOGIC INPUTS

Input High Voltage, VINH

1.5

Compatible with 1.8 V and 3 V logic

Input Low Voltage, VINL

0.6

Input Current, IINH/IINL

±1

µA

Input Capacitance, CIN

3.0

LOGIC OUTPUTS

Output High Voltage, VOH

DVDD − 0.4

CMOS output selected

Output High Current, IOH

500

µA

Output Low Voltage, VOL

0.4

IOL = 500 µA

POWER SUPPLIES

AVDD

3.135

3.465

DVDD

AVDD

Voltage must equal AVDD

RFVDD

AVDD

Voltage must equal AVDD

AVDD

5.5

4.1

Output Dividers

6 to 36

Each output divide by 2 consumes 6 mA; see

Table 6 for details on the current consumption

as a function of the output power and divider

Rev. 0 | Page 3 of 32

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