K6F2016V4E datasheet(8/9 Pages) SAMSUNG

Teilenummer	K6F2016V4E

Bauteilbeschribung	128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

PDF	9 Pages

Scroll/Zoom	100%

Hersteller	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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CMOS SRAM

K6F2016V4E Family

- 8 -

Revision 1.0

March 2002

Address

Data Valid

UB, LB

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS or LB/UB controlled

VCC

3.0V

2.2V

VDR

CS or LB/UB

GND

Data Retention Mode

≥VCC-0.2V or LB=UB≥Vcc-0.2V

tSDR

tRDR

tAS(3)

K6F2016V4E Datenblatt(PDF) 8 Page - Samsung semiconductor