7

IXD611

© 2007 IXYS CORPORATION All rights reserved

Figure 8. Test circuit for allowable offset supply voltage transient.

V

CH

HGO

HS

V

CL

LGO

HIN

LIN

LS

1k

1k

HIN

LIN

1

2

3

4

VIN+

VOUT-

VOUT+

GND

VOUT-

VOUT+

1uF/35V MLCC

1k

V

CL

1uF/35V MLCC

10uF/35V

15

5.1

1N5817

1N5817

5.1

15

18uH

0.47uF

0.47uF

0.1uF/1kV

Up to 500V

V

CL

1

10

11

12

15

14

5

6

7

8

IXCP

10M90S

1

2

3

30

IXTH14N60P

IXTH14N60P

Figure 9. Test circuit for high frequency, 750kHz, operation.

V

HS

LGO

VCH

VCL

HIN

LIN

LS

HGO

N/C

50

GND

dv/dt slope adjustment

DC_DC Boost

NDY1215C

Vout+

Vout-

TX 30:1

1nF

10V

10V

10uF

Low ESR

15V

10uF

0.1uF

IXDN414

Drive Input

Up to 600V

HGO Out

1.5k 2W

20uF

1kV

10x0.1uF

1kV

100uF 25V

Low ESR

100 ohm

multi turn

IXD611

Measure dV/dt