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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SSM2529ACBZ-R7 Datenblatt(PDF) 32 Page - Analog Devices |
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SSM2529ACBZ-R7 Datenblatt(HTML) 32 Page - Analog Devices |
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32 / 52 page  SSM2529 Data Sheet Rev. 0 | Page 32 of 52 Bits Bit Name Settings Description Reset Access 2 PDP_VOL_FORCE PDP volume fade enable 0x0 RW 0 Soft (default) 1 Force 1 DIG_VOL_FORCE DIG volume fade enable 0x0 RW 0 Soft (default) 1 Force 0 ANA_GAIN Analog gain control 0x0 RW 0 3.6 V gain 1 5 V gain DPLL_CTRL REGISTER Table 56. Address: 0x08, Reset: 0x00, Name: DPLL_CTRL Bits Bit Name Settings Description Reset Access 7 Reserved Reserved 0x0 RW [6:4] DPLL_REF_SEL DPLL source clock selection 0x0 RW 000 Select MCLK as DPLL reference clock 001 Select BCLK as DPLL reference clock 010 Select LRCLK as DPLL reference clock [3:0] DPLL_NDIV DPLL output clock frequency 0x0 RW 0000 Reference clock frequency × 1 0001 Reference clock frequency × 1024 0010 Reference clock frequency × 512 0011 Reference clock frequency × 256 0100 Reference clock frequency × 128 0101 Reference clock frequency × 64 0110 Reference clock frequency × 32 0111 Reference clock frequency × 16 1000 Reference clock frequency × 8 1001 Reference clock frequency × 4 1010 Reference clock frequency × 2 APLL_CTRL1 REGISTER Table 57. Address: 0x09, Reset: 0x00, Name: APLL_CTRL1 Bits Bit Name Description Reset Access [7:0] M_HI Denominator (M) of the fractional APLL upper byte 0x00 RW APLL_CTRL2 REGISTER Table 58. Address: 0x0A, Reset: 0x00, Name: APLL_CTRL2 Bits Bit Name Description Reset Access [7:0] M_LO Denominator (M) of the fractional APLL lower byte 0x00 RW APLL_CTRL3 REGISTER Table 59. Address: 0x0B, Reset: 0x00, Name: APLL_CTRL3 Bits Bit Name Description Reset Access [7:0] N_HI Numerator (N) of the fractional APLL upper byte 0x00 RW APLL_CTRL4 REGISTER Table 60. Address: 0x0C, Reset: 0x00, Name: APLL_CTRL4 Bits Bit Name Description Reset Access [7:0] N_LO Numerator (N) of the fractional APLL lower byte 0x00 RW |
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