LTC2605IGN datasheet(12/16 Pages) LINER

12 / 16 page

LTC2605/LTC2615/LTC2625

2605f

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The first four commands in the table

consist of write and update operations. A write operation

loads the 16-bit data word from the 32-bit shift register

into the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path and

registers are shown in the block diagram.

Table 2. Slave Address Map

CA2

CA1

CA0

SA6

SA5

SA4

SA3

SA2

SA1

SA0

GND

0010000

GND

FLOAT

0010001

GND

VCC

0010010

GND

FLOAT

GND

0010011

GND

FLOAT FLOAT

0100000

GND

FLOAT

VCC

0100001

GND

VCC

GND

0100010

GND

VCC

FLOAT

0100011

GND

VCC

0110000

FLOAT

GND

0110001

FLOAT

GND

FLOAT

0110010

FLOAT

GND

VCC

0110011

FLOAT FLOAT

GND

1000000

FLOAT FLOAT FLOAT

1000001

FLOAT FLOAT

VCC

1000010

FLOAT

VCC

GND

1000011

FLOAT

VCC

FLOAT

1010000

FLOAT

VCC

1010001

VCC

GND

1010010

VCC

GND

FLOAT

1010011

VCC

GND

VCC

1100000

VCC

FLOAT

GND

1100001

VCC

FLOAT FLOAT

1100010

VCC

FLOAT

VCC

1100011

VCC

GND

1110000

VCC

FLOAT

1110001

VCC

1110010

GLOBAL ADDRESS

1110011

Power Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than eight outputs are needed. When in power-down, the

buffer amplifiers and reference inputs are disabled and

draw essentially zero current. The DAC outputs are put into

a high-impedance state, and the output pins are passively

pulled to ground through individual 90k resistors. When

all eight DACs are powered down, the bias generation

circuit is also disabled. Input- and DAC- registers are not

disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in

combination with the appropriate DAC address, (n). The

16-bit data word is ignored. The supply and reference

currents are reduced by approximately 1/8 for each DAC

powered down; the effective resistance at REF (Pin 6) rises

accordingly, becoming a high-impedance input (typically

>1G

Ω) when all eight DACs are powered down.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output

is updated.

There is an initial delay as the DAC powers up before it

begins its usual settling behavior. If less than eight DACs

are in a powered-down state prior to the updated

command, the power-up delay is 5

µs. If, on the other

hand, all eight DACs are powered down, then the bias

generation circuit is also disabled and must be restarted.

In this case, the power-up delay is greater: 12

µs for

VCC = 5V, 30µs for VCC = 3V.

Voltage Outputs

Each of the eight rail-to-rail amplifiers contained in these

parts has guaranteed load regulation when sourcing or

sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier’s ability

to maintain the rated voltage accuracy over a wide range

of load conditions. The measured change in output voltage

per milliampere of forced load current change is

expressed in LSB/mA.

OPERATIO

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