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AD5380 Datenblatt(PDF) 9 Page - Analog Devices

Teilenummer AD5380
Bauteilbeschribung  40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC
PDF  34 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5380 Datenblatt(HTML) 9 Page - Analog Devices

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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
AD5380
–9–
PARALLEL INTERFACE
Parameter
1,2,3
Limit at TMIN, TMAX
Units
Description
t0
4.5
ns min
REG0,REG1,Address to
WR Rising Edge Setup Time
t1
4.5
ns min
REG0,REG1, Address to
WR Rising Edge Hold Time
t2
20
ns min
CS Pulse Width Low
t3
20
ns min
WR Pulse Width Low
t4
0
ns min
CS to WR Falling Edge Setup Time
t5
0
ns min
WR to CS Rising Edge Hold Time
t6
4.5
ns min
Data to
WR Rising Edge Setup Time
t7
4.5
ns min
Data to
WR Rising Edge Hold Time
t8
20
ns min
WR Pulse Width High
t9
4
430
ns min
Minimum
WR Cycle Time (Single Channel Write)
t10
4
30
ns max
WR Rising Edge to BUSY Falling Edge
t11
4,5
400
ns max
BUSY Pulse Width Low (Single Channel Update)
t12
4
30
ns min
WR Rising Edge to LDAC Falling Edge
t13
20
ns min
LDAC Pulse Width Low
t14
4
100
ns max
BUSY Rising Edge to DAC Output Response Time
t15
20
ns min
LDAC Rising Edge to WR Rising Edge
t16
0
ns min
BUSY Rising Edge to LDAC Falling Edge
t17
4
100
ns min
LDAC Falling Edge to DAC Output Response Time
t18
8
µs typ
DAC Output Settling Time, Boost Mode Off.
t19
20
ns min
CLR Pulse Width Low
t20
12
µs max
CLR Pulse Activation Time
(DVDD = 2.7 V to +5.5V; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND = DGND = 0 V;
All specifications TMIN to TMAX unless otherwise noted.)
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with t
r = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3See Timing Diagram in Figure 6.
4See Table XXX.
5This is measured with the load circuit of Figure 1a.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Figure 6. Parallel Interface Timing Diagram
t4
t7
t6
DB13..DB0
t5
REG0, REG1, A5..A0
CS
LDAC1
t2
CLR
t20
t19
t3
WR
t10
LDAC2
1
LDAC ACTIVE DURING BUSY
2
LDAC ACTIVE AFTER BUSY
VOUT
1
t17
VOUT
2
t8
BUSY
t11
t12
t13
t13
t16
t14
t18
t18
VOUT
t9
t1
t0
t15



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