AD5380EB datasheet(17/34 Pages) AD

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PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

AD5380

–17–

FUNCTIONAL DESCRIPTION

DAC Architecture — General

The AD5380 is a complete single supply, 40-channel,

voltage output DAC offering 14-bit resolution, available

in a 100 lead LQFP package and features both a parallel

and serial interfaces. This family includes an internal

1.25/2.5V, 10ppm/°C reference that can be used to drive

the buffered reference inputs, alternatively an external

reference can be used to drive these inputs. Reference

selection is via a bit in the control register. All channels

have an on-chip output amplifier with rail-to-rail output

capable of driving a 5k

Ω ohm in parallel with a 200pf

load.

The architecture of a single DAC channel consists of a

14-bit resistor-string DAC followed by an output buffer

amplifier operating at a gain of two. This resistor-string

architecture guarantees DAC monotonicity. The 14-bit

binary digital code loaded to the DAC register determines

at what node on the string the voltage is tapped off before

being fed to the output amplifier. Each channel on these

devices contains independant offset and gain control

registers allowing the user to digitally trim offset and gain.

The inclusion of these registers allows the user the ability

to calibrate out errors in the complete signal chain

including the DAC using the internal M and C registers

which hold the correction factors. All channels are double

buffered allowing synchronous updating of all channels

using the

LDAC pin. Figure 7 shows a block diagram of

a single channel on the AD5380.

The digital input transfer function for each DAC can be

represented as:

x2 = [(m + 1 )/8192 × x1] + (c-2

n-1)

x2 is the Dataword loaded to the resistor string DAC

x1 is the 14-bit Dataword written to the DAC input

m is the13-bit Gain Coefficient (default is all 1FFF Hex

on the AD5380. The gain coefficient is written to the 13

most significant bits. If a 14 bit data word is provided to

the m register the lsb of the data word will be a zero.

n=DAC resolution (n=14 for AD5380)

c is the14-bit Offset Coefficient (default is 2000Hex on

the AD5380)

The complete transfer function for these devices can be

represented as:

VOUT = 2 × VREF

× x2/2

x2 is the Dataword loaded to the resistor string DAC

VREF is the reference voltage applied to the DAC, 2.5V for

specified performance.

Data Decoding

The AD5380 contains a 14-bit data bus, DB13-DB0.

Depending on the value of REG1 and REG0 outlined in

Table 1, this data is loaded into the addressed DAC input

The

format data, Offset (c) and gain (m) register contents

are outlined in tables II to IV.

x1 INPUT

REG

m REG

c REG

DAC

REG

14-BIT

DAC

INPUT

DATA

AVDD

VOUT

VREF

Figure 7. Single Channel Architecture

DB13 to DB0

DAC Output

11 1111 1111 1111

2 VREF × (16383/16384) V

11 1111 1111 1110

2 VREF × (16382/16384)V

10 0000 0000 0001

2 VREF × (8193/16384) V

10 0000 0000 0000

2 VREF × (8192/16384) V

01 1111 1111 1111

2 VREF × (8191/16384) V

00 0000 0000 0001

2 VREF × (1/16384) V

00 0000 0000 0000

Table II. DAC Data format (REG1 = 1, REG0 = 1)

REG1 REG0

Input Data Register (x1)

Offset Register (c)

Gain Register (m)

Special Function Registers (SFRs)

Table I. Register Selection

DB13 to DB1

Gain Factor

1 1111 1111 1111

1 0111 1111 1111

0.75

0 1111 1111 1111

0.5

0 0111 1111 1111

0.25

0 0000 0000 0000

Table IV. Gain Data format (REG1 = 0, REG0 = 1)

DB13 to DB0

Offset

11 1111 1111 1111

+8191LSB

11 1111 1111 1110

+8190LSB

10 0000 0000 0001

+ 1

L S B

10 0000 0000 0000

+ 0

L S B

01 1111 1111 1111

- 1

L S B

00 0000 0000 0001

-8191

L S B

00 0000 0000 0000

-8192

L S B

Table III. Offset Data format (REG1 = 1, REG0 = 0)

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