M24256-BRBN6TP datasheet(9/25 Pages) STMICROELECTRONICS

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M24128-BW, M24128-BR, M24256-BW, M24256-BR

with NoAck, and the location is not modified. If, in-

stead, the addressed location is not Write-protect-

ed, the device replies with Ack. The bus master

terminates the transfer by generating a Stop con-

dition, as shown in Figure 7..

Page Write

The Page Write mode allows up to 64 bytes to be

written in a single Write cycle, provided that they

are all located in the same ’row’ in the memory:

that is, the most significant memory address bits,

b15-b6, are the same. If more bytes are sent than

will fit up to the end of the row, a condition known

as ‘roll-over’ occurs. This should be avoided, as

data starts to become overwritten in an implemen-

tation dependent way.

The bus master sends from 1 to 64 bytes of data,

each of which is acknowledged by the device if

Write Control (WC) is Low. If Write Control (WC) is

High, the contents of the addressed memory loca-

tion are not modified, and each data byte is fol-

lowed by a NoAck. After each byte is transferred,

the internal byte address counter (the 6 least sig-

nificant address bits only) is incremented. The

transfer is terminated by the bus master generat-

ing a Stop condition.

Figure 7. Write Mode Sequences with WC=0 (data write enabled)

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01106C

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

R/W

ACK

R/W

ACK

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