NUC505-YO2T datasheet(69/130 Pages) NUVOTON

69 / 130 page

NUC505

July. 26, 2018

Page 69 of 130

Rev.1.08

FUNCTIONAL DESCRIPTION

ARM

® Cortex® -M4 Core

6.1

The Cortex

® -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA

AHB-Lite interfaces for best parallel performance and includes a NVIC component. The processor

has optional hardware debug functionality, which can execute Thumb code, and is compatible

with other Cortex

® -M profile processors. The profile supports two modes -Thread mode and

Handler mode. Handler mode is entered as a result of an exception. An exception return can only

be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of

an exception return. The Cortex

® -M4F is a processor with the same capability as the Cortex® -M4

processor and includes floating point arithmetic functionality. The NUC505 is embedded with

Cortex

® -M4F processor. Throughout this document the name Cortex® -M4 refers to both Cortex® -

M4 and Cortex

® -M4F processors. The following figure shows the functional controller of the

processor.

Figure 6.1-1 Cortex

® -M4 Block Diagram

Cortex

® -M4 processor features:

 A low gate count processor core, with low latency interrupt processing that has:

─

A subset of the Thumb instruction set, defined in the ARMv7-M Architecture

Reference Manual.

NUC505-YO2T Datenblatt(PDF) 69 Page - Nuvoton Technology Corporation