MPC7455 datasheet(29/64 Pages) FREESCALE

Teilenummer	MPC7455

Bauteilbeschribung	RISC Microprocessor Hardware Specifications

PDF	64 Pages

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Hersteller	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 11 shows the typical connection diagram for the MPC7455 interfaced to PB2 SRAMs, such as the Freescale

MCM63R737, or late write SRAMs, such as the Freescale MCM63R836A.

Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface

L3_ADDR[16:0]

L3_CNTL[0]

SA[16:0]

SRAM 0

DQ[0:17]

DQ[18:36]

L3_CNTL[1]

GVDD/2

GND

SRAM 1

GVDD/2

GND

{L3_DATA[0:15],

{L3_DATA[16:31],

{L3_DATA[32:47],

L3_CLK[0]

L3_CLK[1]

L3_ECHO_CLK[0]

L3_ECHO_CLK[1]

L3_ECHO_CLK[2]

{L3_DATA[48:63],

L3_DP[0:1]}

L3_DP[2:3]}

L3_DP[4:5]}

L3_DP[6:7]}

Denotes

Receive (SRAM

to MPC7455)

Aligned Signals

MPC7455

Denotes

Transmit

(MPC7455 to

SRAM)

Aligned Signals

L3_ECHO_CLK[3]

SA[16:0]

DQ[0:17]

DQ[18:36]

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

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