M50FLW080A datasheet(30/64 Pages) STMICROELECTRONICS

30 / 64 page

Command interface

M50FLW080A, M50FLW080B

30/64

Table 13.

Commands

Command

Bus operations(1)

1st

2nd

3rd

4th

5th

Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read Memory Array(2),(3),(4)

FFh

Read

Addr

Read

Data

(Read

Addr2)

(Read

Data2)

(Read

Addr3)

(Read

Data3)

(Read

Addr4)

(Read

Data4)

Read Status Register(5),(3)

70h

Status

Reg

(X)

(Status

Reg)

(X)

(Status

Reg)

(X)

(Status

Reg)

Read Electronic Signature(3)

90h or

98h

Sig

Addr

Signat

ure

(Sig

Addr)

(Signat

ure)

(Sig

Addr)

(Signatu

re)

(Sig

Addr)

(Signat

ure)

Program / Multiple Byte

program (FWH)(6),(7),(4)

40h or

10h

Prog

Addr

Prog

Data

Quadruple Byte Program

(A/A Mux)(6),(8)

30h

Prog

Data1

Prog

Data2

Prog

Data3

Prog

Data4

Chip Erase(6)

80h

10h

Block Erase(6)

20h

D0h

Sector Erase(6)

32h

D0h

Clear Status Register(9)

50h

Program/Erase suspend(10)

B0h

Program/Erase resume(11)

D0h

Invalid reserved(12)

00h

01h

60h

2Fh

C0h

For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read

Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles

are WRITE.

BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC

mode), and A21 and A20 are set according to the rules shown in Table 5 (for LPC mode)

After a Read Memory Array command, read the memory as normal until another command is issued.

“1+” indicates that there is one write cycle, followed by any number of read cycles.

Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read

Operation is all that is needed.

After a Read Status Register command, read the Status Register as normal until another command is issued.

After the erase and program commands read the Status Register until the command completes and another command is

issued.

Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t

Care. PD is two or four Bytes depending on Msize code.

Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.

After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.

10. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during

Erase Suspend) and Program/Erase Resume commands can be issued.

11. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status

12. Do not use Invalid or Reserved commands.

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