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54HC595 Datenblatt(PDF) 6 Page - Silicon Supplies

Teilenummer 54HC595
Bauteilbeschribung  8-bit shif t registers with 3-state output latches in bare die form
PDF  9 Pages
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54HC595 Datenblatt(HTML) 6 Page - Silicon Supplies

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AC Electrical Characteristics continued6
High Speed CMOS Logic – 54HC595
Rev 1.0
05/02/19
7. Used to determine the no-load dynamic power consumption: PD = CPD VCC
2f + ICC VCC
LIMITS
PARAMETER
SYMBOL
VCC
CONDITIONS
25°C
85°C
FULL RANGE
5
UNITS
2.0V
150
190
225
3.0V
100
125
150
4.5V
30
38
45
Maximum Propagation
Delay, OE to QA – QH
(Figure 4,8)
tPLZ, tPHZ
6.0V
CL = 50pF,
Input
tr = tf = 6ns
26
33
38
ns
2.0V
135
170
205
3.0V
90
110
130
4.5V
27
34
41
Maximum Propagation
Delay, OE to QA – QH
(Figure 4,8)
tPZL, tPZH
6.0V
CL = 50pF,
Input
tr = tf = 6ns
23
29
35
ns
2.0V
60
75
90
3.0V
23
27
31
4.5V
12
15
18
Maximum Output
Transition Time,
QA – QH
(Figure 3,7)
tTLH, tTHL
6.0V
CL = 50pF,
Input
tr = tf = 6ns
10
13
15
ns
2.0V
75
95
110
3.0V
27
32
36
4.5V
15
19
22
Maximum Output
Transition Time,
QH’
(Figure 1,7)
tTLH, tTHL
6.0V
CL = 50pF,
Input
tr = tf = 6ns
13
16
19
ns
Maximum Input
Capacitance
CIN
-
-
10
10
10
pF
Maximum Three-State
Output Capacitance,
QA – QH
COUT
-
High-
Impedance
Output State
15
15
15
pF
TYPICAL
Power Dissipation
Capacitance
7
CPD
-
TJ = 25°C,
VCC = 5.0V
300
pF
Timing Requirements6
LIMITS
PARAMETER
SYMBOL
VCC
CONDITIONS
25°C
85°C
FULL RANGE
5
UNITS
2.0V
50
65
75
3.0V
40
50
60
4.5V
10
13
15
Minimum Setup Time,
SER
to SRCLK
(Figure 5)
tsu
6.0V
Input
tr = tf = 6ns
9
11
13
ns
2.0V
75
95
110
3.0V
60
70
80
4.5V
15
19
22
Minimum Setup Time,
SRCLK
to RCLK
(Figure 6)
tsu
6.0V
Input
tr = tf = 6ns
13
16
19
ns



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