AW9119 datasheet(13/42 Pages) AWINIC

13 / 42 page

AW9119

June 2018 V1.2

www.awinic.com.cn

SCL

SDA

S/Sr

S: START condition

Sr: START Repeated condition

P: STOP condition

Figure 8

I2C Start/Stop Condition Timing

9.3.5

Write Cycle

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction.

New data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and

a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow.

In a write process, the following steps should be followed:

Master device generates START condition. The

“START” signal is generated by lowering the SDA

signal while the SCL signal is high.

Master device sends slave address (7-bit) and the data direction bit (w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8-bit)

Slave sends acknowledge signal

Master sends data high 8Bit to be written to the addressed register

Slave sends acknowledge signal

Master sends data low 8Bit to be written to the addressed register

Slave sends acknowledge signal

Master generates STOP condition to indicate write cycle end

D13 D12

D10

D11

D14

D15

...

SCL

SDA

Ack

Start

R/W

……

Stop

I2C Address

Figure 9

AW9119 I2C Write Timing

9.3.6

Read Cycle

In a read cycle, the following steps should be followed:

Master device generates START condition

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