AW9203

June 2018 V1.2

www.awinic.com.cn

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Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD

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FUNCTIONAL DESCRIPTION

9.1

WORK MODE

Shutdown

PDN=0

VBAT Power On

Internal LDO shutdown,

minimum power dissipation

PDN=1

Registers

Initialization

LDO enable,

powering internal

digital module,

I

Standby

I

Touch detection disable

Active

I

Touch detection enable

PDN=0

PDN=0

Software

Reset

SENE=1

SENE=0

Delay 5ms

Figure 4

AW9203 Work Mode

After VBAT powered on, if PDN pin is low, the AW9203 is in shut-down mode, the current consumption is less

than 15

A. When PDN pin becomes high, the internal LDO is activated, and a power-on reset (POR) signal is

generated to initialize all internal registers, the device enters standby mode, this is a low power consumption

register can be written. If control bit GCR.SENE is written high, the device enters the active mode.

9.2

RESET

9.2.1

Hardware Reset

When PDN pin changes from low to high, the power-up reset (POR) signal is generated, all internal registers

are reset.

9.2.2

Software Reset

to reset all internal registers.

9.3

AW9203 supports the I²C serial bus and data transmission protocol in fast mode at 400kHz. It operates as a

slave on the I²C bus. Connections to the bus are made via the open-drain I/O pins SCL and SDA. The pull-up

resistor can be selected in the range of 1k~10k

Ω and the typical value is 4.7kΩ. AW9203 can support different

9.3.1

Device Address