SC16C554DB datasheet(9/51 Pages) PHILIPS

9 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

9 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

5.2 Pin description

Table 2:

Pin description

Symbol

Type

Description

PLCC68

LQFP64

LQFP80

16/68

16/68 Interface type select (input with internal pull-up). This

input provides the 16 (Intel) or 68 (Motorola) bus interface type

select. The functions of IOR, IOW, INTA to INTD, and CSA to CSD

are re-assigned with the logical state of this pin. When this pin is a

logic 1, the 16 mode interface (16C554) is selected. When this pin

is a logic 0, the 68 mode interface (68C554) is selected. When this

pin is a logic 0, IOW is re-assigned to R/W, RESET is re-assigned

to RESET, IOR is not used, and INTA to INTD are connected in a

wire-OR conﬁguration. The wire-OR outputs are connected

internally to the open drain IRQ signal output. This pin is not

available on 64-pin packages which operate in the 16 mode only.

Address 0 select bit. Internal registers address selection in 16 and

68 modes.

Address 1 select bit. Internal registers address selection in 16 and

68 modes.

Address 2 select bit. Internal registers address selection in 16 and

68 modes.

A3, A4

20, 50

Address 3 to Address 4 select bits. When the 68 mode is

selected, these pins are used to address or select individual UARTs

(providing CS is a logic 0). In the 16 mode, these pins are

re-assigned as chip selects, see CSB and CSC.

CDA, CDB,

CDC, CDD

9, 27,

43, 61

64, 18,

31, 49

19, 42,

59, 2

Carrier Detect (active LOW). These inputs are associated with

individual UART channels A through D. A logic 0 on this pin

indicates that a carrier has been detected by the modem for that

channel.

Chip Select (active LOW). In the 68 mode, this pin functions as a

multiple channel chip enable. In this case, all four UARTs (A to D)

are enabled when the CS pin is a logic 0. An individual UART

channel is selected by the data contents of address bits A3 to A4.

when the 16 mode is selected (68-pin devices), this pin functions as

CSA (see deﬁnition under CSA, CSB).

CSA, CSB,

CSC, CSD

16, 20,

50, 54

7, 11,

38, 42

28, 33,

68, 73

Chip Select A, B, C, D (active LOW). This function is associated

with the 16 mode only, and for individual channels ‘A’ through ‘D’.

When in 16 mode, these pins enable data transfers between the

user CPU and the SC16C554B/554DB for the channel(s)

addressed. Individual UART sections (A, B, C, D) are addressed by

providing a logic 0 on the respective CSA to CSD pin. When the

68 mode is selected, the functions of these pins are re-assigned.

68 mode functions are described under their respective name/pin

headings.

CTSA, CTSB,

CTSC, CTSD

11, 25,

45, 59

2, 16,

33, 47

23, 38,

63, 78

Clear to Send (active LOW). These inputs are associated with

individual UART channels A to D. A logic 0 on the CTS pin indicates

the modem or data set is ready to accept transmit data from the

SC16C554B/554DB. Status can be tested by reading MSR[4]. This

pin only affects the transmit or receive operations when auto-CTS

function is enabled via MCR[5] for hardware ﬂow control operation.

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