GD25LQ32DNFS datasheet(52/72 Pages) GIGADEVICE

52 / 72 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LQ32D

7.37.

Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its

default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch

status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous

Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).

The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset

(99H)” and the “Reset (99H)” command sequence is as followed: CS# goes low  Sending Enable Reset command 

CS# goes high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command is accepted by

the device, the device will take approximately tRST =30

μs / tRST_E =12ms to reset. During this period, no command will be

accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when

Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status

Figure38. Enable Reset and Reset command Sequence Diagram

Command

66H

CS#

SCLK

High-Z

Command

99H

Figure39. Enable Reset and Reset command Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

66H

Command

99H

GD25LQ32DNFS Datenblatt(PDF) 52 Page - GigaDevice Semiconductor (Beijing) Inc.