AMD

P R E L I M I N A R Y

11

Am79C987

Table 1. Summary of All the HIMIB Device Registers

Register

Bytes

Access

Status Register

Note: Read the C Port for Status

1

R

No Need to Specify the Port or Register Number

Port/Register Bank

P[4:0]

Register

R[4:0]

Bytes

Access

Repeater Registers

0

Source Address Match

10

6

R/W

Total Octets

12

4

R

Transmit Collisions

13

4

R

Configuration Register

16

1

R/W

Version/Device ID

28

1

R

IMR+ Management Port Set Register

30

1

W

IMR+ Management Port Get Register

31

1

R/W

Port Status Registers

1

TP Partition Status Change

0

1

R

AUI Partition Status Change

1

1

R

TP Link Status Change

2

1

R

AUI Loop Back Error

3

1

R

Reserved

4

AUI SQE Test Error

5

1

R

TP Source Address Change

6

1

R

AUI Source Address Change

7

1

R

TP Source Address Match Status

8

1

R

AUI Source Address Match Status

9

1

R

Port Control Registers

2

TP Partition Change Interrupt Enable

0

1

R/W

AUI Partition Change Interrupt Enable

1

1

R/W

TP Link Status Change Interrupt Enable

2

1

R/W

AUI Loop Back Error Interrupt Enable

3

1

R/W

Reserved

4

AUI SQE Test Error Interrupt Enable

5

1

R/W

TP Source Address Change Interrupt Enable

6

1

R/W

AUI Source Address Change Interrupt Enable

7

1

R/W

Attribute Registers

16–23, 31

Readable Frames

0

4

R

Readable Octets

1

4

R

Frame Check Sequence Errors

2

4

R

Alignment Errors

3

4

R

Frames Too Long

4

4

R

Short Events

5

4

R

Runts

6

4

R

Collisions

7

4

R

Late Events

8

4

R

Very Long Events

9

4

R

Data Rate Mismatches

10

4

R

Auto Partitions

11

4

R

Source Address Changes

12

4

R

Reserved

13

Last Source Address

14

6

R/W

Note that all register locations listed as reserved and those which might be accessed by values or combinations of P and R which

are not listed in the table above should not be accessed by the software. Read/write access to reserved registers may cause

incorrect operation.