GD25Q64CSFS datasheet(16/74 Pages) GIGADEVICE

Teilenummer	GD25Q64CSFS

Bauteilbeschribung	3.3V Uniform Sector Dual and Quad Serial Flash

PDF	74 Pages

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Hersteller	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Direct Link	http://www.gigadevice.com/

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16 / 74 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q64C

7.1.

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must

be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register

(WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low

 sending the Write Enable command  CS# goes high.

Figure 2. Write Enable Sequence Diagram

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS#

goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up

and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program

Security Registers and Reset commands.

Figure 3. Write Disable Sequence Diagram

Command

06H

CS#

SCLK

High-Z

Command

04H

CS#

SCLK

High-Z

GD25Q64CSFS Datenblatt(PDF) 16 Page - GigaDevice Semiconductor (Beijing) Inc.