TMS320DM643 datasheet(1/160 Pages) TI

Teilenummer	TMS320DM643

Bauteilbeschribung	Video/Imaging Fixed-Point Digital Signal Processo

PDF	160 Pages

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Hersteller	TI [Texas Instruments]

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TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor

1.1

Features

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

–

1024M-Byte Total Addressable External

• High-Performance Digital Media Processor

Memory Space

–

2-, 1.67-ns Instruction Cycle Time

• Enhanced Direct-Memory-Access (EDMA)

–

500-, 600-MHz Clock Rate

Controller (64 Independent Channels)

–

Eight 32-Bit Instructions/Cycle

• 10/100 Mb/s Ethernet MAC (EMAC)

–

4000, 4800 MIPS

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IEEE 802.3 Compliant

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Fully Software-Compatible With C64x™

–

Media Independent Interface (MII)

• VelociTI.2™ Extensions to VelociTI™

–

8 Independent Transmit (TX) Channels and

Advanced Very-Long-Instruction-Word (VLIW)

1 Receive (RX) Channel

TMS320C64x™ DSP Core

• Management Data Input/Output (MDIO)

–

Eight Highly Independent Functional Units

With VelociTI.2™ Extensions:

• Two Configurable Video Ports (VP1, VP2)

• Six ALUs (32-/40-Bit), Each Supports

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Providing a Glueless I/F to Common Video

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Decoder and Encoder Devices

Arithmetic per Clock Cycle

–

Supports Multiple Resolutions/Video Stds

• Two Multipliers Support Four 16 x 16-Bit

• VCXO Interpolated Control Port (VIC)

Multiplies (32-Bit Results) per Clock

–

Supports Audio/Video Synchronization

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

• Host-Port Interface (HPI) [32-/16-Bit]

Results) per Clock Cycle

–

Load-Store Architecture With Non-Aligned

• Multichannel Audio Serial Port (McASP)

Support

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Eight Serial Data Pins

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64 32-Bit General-Purpose Registers

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Wide Variety of I2S and Similar Bit Stream

–

Instruction Packing Reduces Code Size

Format

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All Instructions Conditional

–

Integrated Digital Audio I/F Transmitter

Supports S/PDIF, IEC60958-1, AES-3,

• Instruction Set Features

CP-430 Formats

–

Byte-Addressable (8-/16-/32-/64-Bit Data)

• Inter-Integrated Circuit (I2C Bus™)

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8-Bit Overflow Protection

• Multichannel Buffered Serial Port

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Bit-Field Extract, Set, Clear

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CLKS Input Not Supported

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Normalization, Saturation, Bit-Counting

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VelociTI.2™ Increased Orthogonality

• Three 32-Bit General-Purpose Timers

• L1/L2 Memory Architecture

• Sixteen General-Purpose I/O (GPIO) Pins

–

128K-Bit (16K-Byte) L1P Program Cache

• Flexible PLL Clock Generator

(Direct Mapped)

• IEEE-1149.1 (JTAG) Boundary-

–

128K-Bit (16K-Byte) L1D Data Cache (2-Way

Scan-Compatible

Set-Associative)

• 548-Pin Ball Grid Array (BGA) Package

–

2M-Bit (256K-Byte) L2 Unified Mapped

(GDK and ZDK Suffixes), 0.8-mm Ball Pitch

RAM/Cache (Flexible RAM/Cache

• 548-Pin Ball Grid Array (BGA) Package

Allocation)

(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch

• Endianess: Little Endian, Big Endian

• 0.13-µm/6-Level Cu Metal Process (CMOS)

• 64-Bit External Memory Interface (EMIF)

• 3.3-V I/O, 1.2-V Internal (-500)

–

Glueless Interface to Asynchronous

Memories (SRAM and EPROM) and

• 3.3-V I/O, 1.4-V Internal (-600)

Synchronous Memories (SDRAM, SBSRAM,

ZBT SRAM, and FIFO)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a registered trademark of Microsoft Corporation.

I2C Bus is a trademark of Philips Electronics N.V.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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