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ST72311 Datenblatt(PDF) 69 Page - STMicroelectronics |
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ST72311 Datenblatt(HTML) 69 Page - STMicroelectronics |
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69 / 94 page ![]() 69/94 ST72311 SERIAL PERIPHERAL INTERFACE (Cont’d) Status Register (SR) Read Only Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register). 0: Data transfer is in progress or has been ap- proved by a clearing sequence. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 39). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 4.5.4.5 Master Mode Fault). An SPI interrupt can be gen- erated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. Data I/O Register (DR) Read/Write Reset Value: Undefined The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/re- ception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data di- rectly into the shift register for transmission. A read to the DR register returns the value located in the buffer and not the contents of the shift regis- ter (see Figure 36). Table 19. SPI Register Map and Reset Values 70 SPIF WCOL - MODF - - - - 70 D7 D6 D5 D4 D3 D2 D1 D0 Address (Hex.) Register Name 76 54 32 10 21 DR Reset Value D7 x D6 x D5 x D4 x D3 x D2 x D1 x D0 x 22 CR Reset Value SPIE 0 SPE 0 SPR2 0 MSTR 0 CPOL x CPHA x SPR1 x SPR0 x 23 SR Reset Value SPIF 0 WCOL 0 - 0 MODF 0 - 0 - 0 - 0 - 0 69 |
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