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UPD4483362 Datenblatt(PDF) 9 Page - NEC |
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UPD4483362 Datenblatt(HTML) 9 Page - NEC |
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9 / 16 page ![]() 9 µPD4483362 Preliminary Data Sheet M14440EJ1V0DS Single Differential Clock, Registered Input / Registered Output Mode Parameter Symbol –A75 (133 MHz) Unit Notes MIN. MAX. Clock cycle time tKHKH 7.5 – ns Clock phase time tKHKL / 2.0 – ns tKLKH Setup times Address tAVKH 1.5 – ns Write data tDVKH Write enable tWVKH Chip select tSVKH Hold times Address tKHAX 0.5 – ns Write data tKHDX Write enable tKHWX Chip select tKHSX Clock access time tKHQV – 3.8 ns 1 K high to Q change tKHQX 1.5 – ns 2 /G low to Q valid tGLQV – 3.8 ns 1 /G low to Q change tGLQX 0 – ns 2 /G high to Q Hi-Z tGHQZ 03.8 ns 2 K high to Q Hi-Z (/SW) tKHQZ 1.5 3.8 ns 2 K high to Q Hi-Z (/SS) tKHQZ2 1.5 3.8 ns 2 K high to Q Lo-Z tKHQX2 1.5 – ns 2 Sleep Mode Recovery tZZR – 7.5 ns Sleep Mode Enable tZZE – 7.5 ns Notes 1. See figure. (VTT = 0.75 V) DQ (Output) ZO = 50 Ω 20 pF 50 Ω VTT 2. See figure. (VTT = 0.75 V) DQ (Output) 5 pF 50 Ω VTT |
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