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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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MM54HCT573 Datenblatt(PDF) 3 Page - National Semiconductor (TI) |
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MM54HCT573 Datenblatt(HTML) 3 Page - National Semiconductor (TI) |
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3 / 6 page  AC Electrical Characteristics MM54HCT573MM74HCT573 VCCe50V tretfe6nsTAe25 C (unless otherwise specified) Symbol Parameter Conditions Typ Guaranteed Units Limit tPHL tPLH Maximum Propagation Delay CLe45 pF 17 27 ns Data to Output tPHL tPLH Maximum Propagation Delay CLe45 pF 16 27 ns Latch Enable to Output tPZH tPZL Maximum Enable Propagation Delay CLe45 pF 21 30 ns Control to Output RLe1kX tPHZ tPLZ Maximum Disable Propagation Delay CLe5pF 14 23 ns Control to Output RLe1kX tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 5 ns tH Minimum Hold Time Clock to Data 12 ns AC Electrical Characteristics MM54HCT573MM74HCT573 VCCe50V g10% tretfe6 ns (unless otherwise specified) TAe25 C 74HCT 54HCT Symbol Parameter Conditions TAeb40 to 85 CTAeb55 to 125 C Units Typ Guaranteed Limits tPHL tPLH Maximum Propagation CLe50 pF 18 30 38 45 ns Delay Data to Output tPHL tPLH Maximum Propagation Delay CLe50 pF 17 30 44 53 ns Latch Enable to Output tPZH tPZL Maximum Enable Propagation CLe50 pF 22 30 38 45 ns Delay Control to Output RLe1kX tPHZ tPLZ Maximum Disable Propagation CLe50 pF 15 30 38 45 ns Delay Control to Output RLe1kX tTHL tTLH Maximum Output Rise and Fall Time CL e 50 pF 6 12 15 18 ns tW Minimum Clock Pulse Width 15 20 24 ns tS Minimum Setup Time Data to Clock b 35 6 8 ns tH Minimum Hold Time Clock to Data 4 12 15 18 ns CIN Maximum Input Capacitance 10 10 10 pF COUT Maximum Output Capacitance 20 20 20 pF CPD Power Dissipation Capacitance (Note 5) OCeVCC 5pF OCeGND 52 pF Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC Truth Table ’HCT573 Output LE Data Output Control LH H H LH L L LL X Q0 HX X Z H e high level L e low level Q0 e level of output before steady-state input conditions were established Z e high impedance ’HCT574 Output Clock Data Output Control L u HH L u LL LL X Q0 HX X Z H e High Level L e Low Level X e Don’t Care u e Transition from low-to-high Z e High impedance state Q0 e The level of the output before steady state input conditions were established 3 |
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