ST7SB20JSLASHEU datasheet(21/154 Pages) STMICROELECTRONICS

21 / 154 page

ST7232A

21/154

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 10.

For more details, refer to dedicated parametric

section.

Main features

■ Optional PLL for multiplying the frequency by 2

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the

range 2 to 4 MHz, the PLL can be used to multiply

the frequency by two to obtain an fOSC2 of 4 to 8

MHz. The PLL is enabled by option byte. If the PLL

is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for appli-

cations where timing accuracy is required.

Figure 9. PLL Block Diagram

Figure 10. Clock, Reset and Supply Block Diagram

PLL OPTION BIT

PLL x 2

fOSC2

/ 2

fOSC

fOSC2

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

VSS

VDD

RESET SEQUENCE

MANAGER

(RSM)

OSC2

MAIN CLOCK

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

WDG

fOSC

(option)

fCPU

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