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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SAFC161PI Datenblatt(PDF) 12 Page - Infineon Technologies AG |
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SAFC161PI Datenblatt(HTML) 12 Page - Infineon Technologies AG |
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12 / 400 page  &3, ,QWURGXFWLRQ User’s Manual 1-4 1999-08 1.2 Summary of Basic Features The C161PI is an improved representative of the Infineon family of full featured 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and means for power reduction. Several key features contribute to the high performance of the C161PI (the indicated timings refer to a CPU clock of 25 MHz). High Performance 16-Bit CPU With Four-Stage Pipeline • 80 ns minimum instruction cycle time, with most instructions executed in 1 cycle • 400 ns multiplication (16-bit *16-bit), 800 ns division (32-bit/16-bit) • Multiple high bandwidth internal data buses • Register based design with multiple variable register banks • Single cycle context switching support • 16 MBytes linear address space for code and data (von Neumann architecture) • System stack cache support with automatic stack overflow/underflow detection Control Oriented Instruction Set with High Efficiency • Bit, byte, and word data types • Flexible and efficient addressing modes for high code density • Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags • Hardware traps to identify exception conditions during runtime • HLL support for semaphore operations and efficient data access Power Management Features • Programmable system slowdown (slowdown divider SDD) • Flexible peripheral management (individual disabling) • Sleepmode including wakeup via external interrupts • Programmable frequency output Integrated On-chip Memory • 1 KByte internal RAM for variables, register banks, system stack and code • 2 KByte on-chip high-speed XRAM for variables, user stack and code External Bus Interface • Multiplexed or demultiplexed bus configurations • Segmentation capability and chip select signal generation • 8-bit or 16-bit data bus • Bus cycle characteristics selectable for five programmable address areas |
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