L6983 datasheet(31/63 Pages) STMICROELECTRONICS

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CR1 capacitor is sometimes useful to increase the small signal phase margin (please refer to the Section

7 Closing the loop).

Figure 29. Application circuit

PGOOD

BOOT

VBIAS

VOUT/FB

PGND

VIN

VINLDO

EN/CLKIN

FSW

VCC

AGND

E.P.

L6983

VOUT

GND

VIN

R FSW

C VCC

CBOOT

RPGOOD

R 2

COUT

CR1

CIN

CFILT

RFILT

8.4

Switching frequency

A resistor connected to the FSW pin features the selection of the switching frequency (refer to the Table 7. FSW

selection).

Connecting the resistor between the pins RFSW and VCC, the internal dithering circuit is turned on. (refer to the

Section 6.6 Spread spectrum).

8.5

Design of the power components

8.5.1

Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.

During the switching activity a pulsed current flows into the input capacitor and so, its RMS current capability must

be selected according to the application conditions. Internal losses of the input filter depends on the ESR value so

usually low ESR capacitors (such as multilayer ceramic capacitors) have higher RMS current capability. On the

other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher

conversion efficiency.

The maximum RMS input current, flowing through the capacitor, can be calculated as follows:

IRMS=IOUT∙ 1−Dη ∙Dη

(33)

Where IOUT is the maximum DC output current, D is the duty cycles, η is the efficiency. This function has a

maximum at D = 0.5 and, considering η = 1, it is equal to IOUT/2. In a specific application, the range of possible

duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and

minimum duty cycles can be calculated as:

DMAX= VOUT+∆VLOWSIDE

VINmin+∆VLOWSIDE−∆VHIGHSIDE

(34)

Dmin= VOUT+∆VLOWSIDE

VINMAX+∆VLOWSIDE−∆VHIGHSIDE

(35)

Where ΔVHIGHSIDE and ΔVLOWSIDE are the voltage drops across the embedded switches. The peak-to-peak

voltage across the input filter can be calculated as the equation below:

VPP= IOUT

CIN∙FSW∙ 1−Dη ∙Dη+ESR∙ IOUT+∆IL

(36)

L6983

Switching frequency

DS13116 - Rev 1

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