STM32MP151A datasheet(41/253 Pages) STMICROELECTRONICS

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DS12500 Rev 3

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STM32MP151A/D

Functional overview

3.28

Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS

sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera

interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock and

14-bit of data. It features:

•

Programmable polarity for the input pixel clock and synchronization signals

•

Parallel data communication can be 8-, 10-, 12- or 14-bit

•

Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2

progressive video, RGB 565 progressive video or compressed data (like JPEG)

•

Supports continuous mode or snapshot (a single frame) mode

•

Capability to automatically crop the image

3.29

LCD-TFT display controller (LTDC)

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)

and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

WXGA (1366×768) @60 fps resolution with the following features:

•

2 display layers with dedicated FIFO

•

Color look-up table (CLUT) up to 256 colors (256×24-bit) per layer

•

Up to 8 input color formats selectable per layer

•

Flexible blending between two layers using alpha value (per pixel or constant)

•

Flexible programmable parameters for each layer

•

Color keying (transparency color)

•

Up to 4 programmable interrupt events

•

AXI master interface

3.30

True random number generator (RNG1, RNG2)

All the devices embed two RNG that deliver 32-bit random numbers generated by an

integrated analog circuit.

RNG1 can be defined (in ETZPC) as accessible by secure software only.

3.31

Hash processors (HASH1, HASH2)

The devices embed two processors that support the advanced algorithms usually required

to ensure authentication, data integrity and non-repudiation when exchanging messages

with a peer:

•

Universal HASH

–

SHA-1, SHA224 and SHA256 (secure HASH algorithms)

–MD5

–HMAC

The accelerator supports DMA request generation.

HASH1 can be defined (in ETZPC) as accessible by secure software only.

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