STM32MP153A datasheet(51/254 Pages) STMICROELECTRONICS

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DS12502 Rev 3

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STM32MP153A/D

Functional overview

frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA

capability.

SPI6 can be defined (in ETZPC) as accessible by secure software only.

3.40

Serial audio interfaces (SAI1, SAI2, SAI3, SAI4)

The devices embed 4 SAIs that allow the design of many stereo or mono audio protocols

such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available

when the audio block is configured as a transmitter. To bring this level of flexibility and

reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own

clock generator and I/O line controller.

Audio sampling frequencies up to 192 kHz are supported.

In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.

The SAI can work in master or slave configuration. The audio sub-blocks can be either

receiver or transmitter and can work synchronously or asynchronously (with respect to the

other one). The SAI can be connected with other SAIs to work synchronously.

3.41

SPDIF receiver interface (SPDIFRX)

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958

and IEC-61937. These standards support simple stereo streams up to high sample rate,

and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up

to 5.1).

The main SPDIFRX features are the following:

•

Up to 4 inputs available

•

Automatic symbol rate detection

•

Maximum symbol rate: 12.288 MHz

•

Stereo stream from 32 to 192 kHz supported

•

Supports audio IEC-60958 and IEC-61937, consumer applications

•

Parity bit management

•

Communication using DMA for audio samples

•

Communication using DMA for control and user channel information

•

Interrupt capabilities

The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and

decode the incoming data stream. The user can select the wanted SPDIF input, and when a

valid signal is available, the SPDIFRX re-samples the incoming signal, decode the

Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the

CPU decoded data, and associated status flags.

The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF

sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.

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