VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC6424

500 Mb/s Video

Shift Register IC

G52236-0, Rev 3.0

© VITESSE SEMICONDUCTOR CORPORATION

Page 3

7/13/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

The Output Phase Shift (OPS) signal gives the capability of selecting which edge of the high speed clock

the DOUT data is synchronized to. When OPS is low, DOUT comes out on the rising edge of CLK. When OPS

is high, DOUT comes out on the falling edge of CLK. The high speed output clock (CLKOUT) is not affected by

the state of OPS.

External Timing

To provide a functional replacement for older designs using the Bt424, formerly manufactured by Brook-

Tree, the VSC6424 provides an external timing mode. This can be accomplished by setting the INT/EXTN pin

low to bypass the internal timing generator. In this case the load and shift timing signals are provided through

the Shift Enable(SEN), Shift Register Load Control(SLDN), and the Latch Load Control(LLDN) pins.

The VSC6424 has two cycles of propagation delay in multiplexer mode where the Bt424 only has one. This

provides the ability to control on which edge of the output clock the output data is clocked on. With the Output

Phase Select (OPS) pin low the output data (DOUT) is synchronous with the positive edge of CLKOUT, where

if OPS is high the output data is synchronous to the negative edge of CLKOUT. See Figure 6 for a timing dia-

gram example with OPS low.

The shift register can also be loaded with serial data while in external timing mode. This is accomplished by

inputting data into the shift register through the Serial Input (SIN) pin. The data is latched on the rising edge of

the CLK while SLDN is high and SEN is low. The data is then shifted to the output pins on each clock cycle

once Shift Enable (SEN) is set high.

I/O Mapping

There are 10 high speed ECL data inputs and 8 high speed ECL data outputs. Some configurations of oper-

ation do not use all these inputs and outputs. The state of the outputs not being used in a given mode is not guar-

anteed. The following two tables, Table 2 and Table 3, show how the high speed bus (DOUT or DIN) maps to

the low speed bus (SB) for a given configuration.

Data is taken and supplied LSB first. The numbers in the table cells refers to the data bit on the low speed

bus (SB<0:39>). They are the inputs in MUX mode and the outputs in DEMUX mode.

Table 2: MUX Mode SB to DOUT Cross Reference

S<2:0>

Modulus

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

000

8 4:1

28-31

24-27

20-23

16-19

12-15

8-11

4-7

0-3

001

8 5:1

35-39

30-34

25-29

20-24

14-19

10-14

5-9

0-4

010

5 8:1

32-39

24-31

16-23

8-15

0-7

011

4 10:1

30-39

20-29

10-19

0-9

100

2 16:1

16-32

0-15

101

2 20:1

20-39

0-19

110

1 32:1

0-31

111

1 40:1

0-39