CDP1824CSLASH3 datasheet(1/5 Pages) INTERSIL

Teilenummer	CDP1824C/3

Bauteilbeschribung	High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory

PDF	5 Pages

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Hersteller	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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42

TM

Features

• Access Time

- 610ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . at VDD = 5V

- 320ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . at VDD = 10V

• No Precharge or Clock Required

Description

The CDP1824/3 and CDP1824C/3 types are high-reliability

CMOS 32-word x 8-bit fully static random-access memories

for use in CDP1800-series microprocessor systems. These

parts are compatible with the CDP1802 microprocessor and

will interface directly without additional components.

The CDP1824/3 is fully decoded and does not require a pre-

charge or clocking signal for proper operation. It has com-

mon input and output and is operated from a single voltage

supply. The MRD signal (output disable control) enables the

three-state output drivers, and overrides the MWR signal. A

CS input is provided for memory expansion.

The CDP1824C/3 is functionally identical to the CDP1824/3.

The CDP1824/3 has a recommended operating voltage

range of 4V to 10.5V, and the CDP1824C/3 has an operating

voltage range of 4V to 6.5V.

Ordering Information

5V

10V

PACK-

AGE

TEMP. RANGE

PKG.

NO.

CDP1824CD3 CDP1824D3 SBDIP

-55oC to

+125oC

D18.3

Pinout

CDP1824/3, CDP1824C/3 (SBDIP)

TOP VIEW

Functional Diagram

10

11

12

13

14

15

16

17

18

9

8

7

6

5

4

3

2

1

VDD

MRD

CS

BUS0

BUS1

BUS2

BUS3

MWR

BUS4

MA4

MA3

MA2

MA1

MA0

BUS7

BUS5

BUS6

VSS

MA4

MA3

MA2

MA1

MA0

MWR

CS

VDD = 18

VSS = 9

BUS

7

BUS

6

BUS

5

BUS

4

BUS

3

BUS

2

BUS

1

BUS

0

MRD

16

5

4

3

21

17

15

6

7

8

1011

1213

14

ADDRESS

DECODER

32 X 8-BIT

ARRAY

SENSE

AMPL

I/O BUFFERS

OPERATIONAL MODES

FUNCTION

CS

MRD

MWR

DATA PINS STATUS

READ

0

X

Output: High/Low Dependent on Data

WRITE

0

1

0

Input: Output Disabled

Not Selected

1

X

Output Disabled: High-Impedance State

Standby

0

1

Output Disabled: High-Impedance State

Logic 1 = High

Logic 0 = Low

X = Don’t Care

March 1997

CDP1824/3,

CDP1824C/3

High-Reliability CMOS 32-Word x 8-Bit

Static Random-Access Memory

File Number

1717.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a trademark of Intersil Americas Inc.

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