TLV4021 datasheet(8/38 Pages) TI

8 / 38 page

OUT

/d5

HYS

PLH

PHL

IT+

TLV4021, TLV4031, TLV4041, TLV4051

SNVSB04B – MARCH 2019 – REVISED JUNE 2020

www.ti.com

Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

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(1)

High-to-low and low-to-high refers to the transition at the input.

(2)

During power on cycle, VS must exceed 1.6 V for tON before the output will reflect the condition on the input. Prior to tON elapsing, the

output is controlled by the POR circuit.

6.6 Switching Characteristics

Typical values are at TA = 25°C, VS = 3.3 V, CL = 15 pF; Input overdrive = 100 mV for TLV40x1Ry & 5% for

TLV4021S5, RP=4.99 kΩ for open-drain options (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPHL

Propagation delay, high-to-low (1)

Midpoint of input to midpoint of output

360

tPLH

Propagation delay, low-to-high (1)

Midpoint of input to midpoint of output

360

tPHL

Propagation delay, high-to-low

(1)(TLV4021S5 only)

Midpoint of input to midpoint of output

µs

tPLH

Propagation delay, low-to-

high (1)(TLV4021S5 only)

Midpoint of input to midpoint of output

µs

Rise time

(TLV4041/4051 only)

20% to 80%

Fall time

20% to 80%

tON

Power-up time (2)

500

µs

Figure 1. Timing Diagram Non-Inverting Input

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