STM32F722IC datasheet(28/229 Pages) STMICROELECTRONICS

28 / 229 page

Functional overview

STM32F722xx STM32F723xx

28/229

DS11853 Rev 6

3.13

Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option

bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF

which includes:

•

All Flash address space mapped on ITCM or AXIM interface

•

All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface

•

The System memory bootloader

The boot loader is located in system memory. It is used to reprogram the Flash memory

through a serial interface.

3.14

Power supply schemes

•

VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins.

•

VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Note:

The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode

versus device operating mode to identify the packages supporting this option.

•

The VDDSDMMC can be connected either to VDD or an external independent power

supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For

example, when the device is powered at 1.8V, an independent power supply 2.7V can

be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power

supply, it is independent from VDD or VDDA but it must be the last supply to be provided

and the first to disappear. The following conditions VDDSDMMC must be respected:

–

During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower

than VDD

–

During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always

lower than VDD

–The VDDSDMMC rising and falling time rate specifications must be respected

–

In the operating mode phase, VDDSDMMC could be lower or higher than VDD:

All associated GPIOs powered by VDDSDMMC are operating between

VDDSDMMC_MIN and VDDSDMMC_MAX.

•

The VDDUSB can be connected either to VDD or an external independent power supply

(3.0 to 3.6V) for USB transceivers (refer to Figure 8 and Figure 9). For example, when

the device is powered at 1.8V, an independent power supply 3.3V can be connected to

the VDDUSB. When the VDDUSB is connected to a separated power supply, it is

independent from VDD or VDDA but it must be the last supply to be provided and the first

to disappear. The following conditions VDDUSB must be respected:

–

During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower

than VDD

–

During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower

than VDD

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