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ASMP5P23S09A Datenblatt(PDF) 4 Page - Alliance Semiconductor Corporation |
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ASMP5P23S09A Datenblatt(HTML) 4 Page - Alliance Semiconductor Corporation |
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4 / 16 page ![]() ASM5P23S09A August 2003 ASM5P23S05A rev 2.0 3.3V ‘SpreadTrak’ Zero Delay Buffer 4 of 16 Notice: The information in this document is subject to change without notice. Pin Description for ASM5P23S09A Pin # Pin Name Description 1 REF 2 Input reference frequency, 5V tolerant input 2 CLKA1 3 Buffered clock output, bank A 3 CLKA2 3 Buffered clock output, bank A 4 VDD 3.3V supply 5 GND Ground 6 CLKB1 3 Buffered clock output, bank B 7 CLKB2 3 Buffered clock output, bank B 8 S2 4 Select input, bit 2 9 S1 4 Select input, bit 1 10 CLKB3 3 Buffered clock output, bank B 11 CLKB4 3 Buffered clock output, bank B 12 GND Ground 13 VDD 3.3V supply 14 CLKA3 3 Buffered clock output, bank A 15 CLKA4 3 Buffered clock output, bank A 16 CLKOUT 3 Buffered output, internal feedback on this pin Pin Description for ASM5P23S05A Pin # Pin Name Description 1 REF 2 Input reference frequency, 5V-tolerant input 2 CLK2 3 Buffered clock output 3 CLK1 3 Buffered clock output 4 GND Ground 5 CLK3 3 Buffered clock output 6 VDD 3.3V supply 7 CLK4 3 Buffered clock output 8 CLKOUT 3 Buffered clock output, internal feedback on this pin Notes: 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs. |
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