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PRELIMINARY
CY28344
Document #: 38-07113, Rev. *A
Page 19 of 22
Layout Example
48
47
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6
7
13
19
20
24
1
2
3
4
5
8
9
11
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15
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22
23
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32
31
18
33
10
28
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29
30
FB
+3.3V Supply
C2
10
µF
FB = Dale ILB1206 – 300 or 2TDKACB2012L – 120 or 2 Murata BLM21B601S
0.005
µF
G
G
VDDQ3
C1
G
V
G
V
G
V
G
V
G
V
G
G
VDDQ3
C5
C6
8Ω
G
V
G
G
G
G
G
V
*Option B
G
G
G
G
G
G
G
G
G
G
G
Core
G
V
G
*Option A
G
Ceramic Caps C1 = 10 – 22
µF C2 = 0.005 µF C5 = 0.1 µF C6 = 10 µF
G = VIA to GND plane layer V = VIA to respective supply plane layer
Note. Each supply plane or strip should have a ferrite bead and capacitors.
* If on-board video uses 48 MHz or Dot clock uses Option B
All bypass caps on VDD pin = 0.1 uF Low ESR