5-1

FAST AND LS TTL DATA

SYNCHRONOUS 4-BIT

UP/DOWN COUNTER

The SN54 / 74LS669 is a synchronous 4-bit up/down counter. The LS669 is

a 4-bit binary counter. For high speed counting applications, this presettable

counter features an internal carry lookahead for cascading purposes. By

clocking all flip-flops simultaneously so the outputs change coincident with

each other (when instructed to do so by the count enable inputs and internal

gating) synchronous operation is provided. This helps to eliminate output

counting spikes, normally associated with asynchronous (ripple-clock) count-

ers. The four master-slave flip-flops are triggered on the rising (positive-going)

edge of the clock waveform by a buffered clock input.

Circuitry of the load inputs allows loading with the carry-enable output of the

cascaded counters. Because loading is synchronous, disabling of the counter

by setting up a low level on the load input will cause the outputs to agree with

the data inputs after the next clock pulse.

Cascading counters for N-bit synchronous applications are provided by the

carry look-ahead circuitry, without additional gating. Two count-enable inputs

and a carry output help accomplish this function. Count-enable inputs (P and

T) must both be low to count. The level of the up-down input determines the

direction of the count. When the input level is low, the counter counts down,

and when the input is high, the count is up. Input T is fed forward to enable the

carry output. The carry output will now produce a low level output pulse with a

duration

≈ equal to the high portion of the QA output when counting up and

when counting down

≈ equal to the low portion of the QA output. This low level

carry pulse may be utilized to enable successive cascaded stages. Regard-

less of the level of the clock input, transitions at the P or T inputs are allowed.

By diode-clamping all inputs, transmission line effects are minimized which

allows simplification of system design.

Any changes at control inputs (ENABLE P, ENABLE T, LOAD, UP/ DOWN)

will have no effect on the operating mode until clocking occurs because of the

fully independant clock circuits. Whether enabled, disabled, loading or count-

ing, the function of the counter is dictated entirely by the conditions meeting

the stable setup and hold times.

CONNECTION DIAGRAM (TOP VIEW)

14

13

12

11

10

9

1

2345

6

7

16

15

8

VCC

U/D

RIPPLE

CARRY

OUTPUT QA

QB

QC

ENABLE

T

QD

LOAD

CK

A

B

C

D

ENABLE

P

GND

UP/DOWN

OUTPUTS

CK

A

B

C

D

ENABLE

P

LOAD

ENABLE

T

RIPPLE

CARRY

OUTPUT

QA

QB

QC

QD

DATA INPUTS

SN54/74LS669

SYNCHRONOUS 4-BIT

UP/DOWN COUNTER

LOW POWER SCHOTTKY

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

16

1

D SUFFIX

SOIC

CASE 751B-03