STM32WL55JC datasheet(39/145 Pages) STMICROELECTRONICS

39 / 145 page

DS13293 Rev 1

39/145

STM32WL55/54xx

Functional overview

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three event flags (DMA half-transfer, DMA transfer complete and DMA transfer error),

logically ORed together in a single interrupt request for each channel

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memory-to-memory transfer

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peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers

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access to Flash memory, SRAM, APB and AHB peripherals, as source and destination

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programmable number of data to be transferred (up to 65536)

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secure and privileged support per channel level configuration

DMAMUX1 is used to route the peripherals with DMA source support, to any DMA channel.

3.18

Interrupts and events

3.18.1

Nested vectored interrupt controller (NVIC)

The devices embed an NIVC able to manage 16 priority levels, and to handle up to

62 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M4.

The device also embeds an NVIC able to manage four priority levels, and handles up to

32 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M0+.

The NVIC benefits are the following:

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low-latency interrupt processing

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interrupt entry vector table address passed directly to the core

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early processing of interrupts

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processing of late-arriving higher-priority interrupts

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support for tail chaining

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processor state automatically saved

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interrupt entry restored on interrupt exit, with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.18.2

Extended interrupt/event controller (EXTI)

The EXTI manages wakeup through configurable and direct event inputs. It provides wake-

up requests to the power control, and generates interrupt requests to the CPU1/2 NVIC and

events to the CPU1/2 event input.

Configurable events/interrupts come from peripherals that are able to generate a pulse and

allow the selection between the event/interrupt trigger edge and a software trigger.

Direct events/interrupts come from peripherals having their own clearing mechanism.

Table 11. DMA1 and DMA2 implementation

Feature

DMA1

DMA2

Number of channels

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