TMP47C101 datasheet(13/32 Pages) TOSHIBA

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TMP47C101/201

2.7.2 Timing Generator

The timing generator produces the system clocks from basic

clock pulse (CP) which are supplied to the SPU and the

peripheral hardware.

The timing generator consists of a 18-stage binary

counter with a divided-by-16 prescaler. The basic clock (fre-

quency: fc) provides the timing generator. Therefore, the out-

put frequency at the last stage is fc/222[Hz]. During reset, the

binary counter is cleared to “0”, however, the prescaler is not

cleared.

Figure 2-16. Conﬁguration of Interval Timer

The timing generator provides the following functions:

Generation of an internal source clock for interval timer

Generation of an internal source clock for timer/

counters

Generation of a warm-up time for releasing of the hold

operating mode

2.7.3 Instruction Cycle

The instruction execution and the on-chip peripheral hardware

operations are performed in synchronization with the basic

clock pulse (CP: fx [Hx]). The smallest unit of instruction execu-

tion is called an instruction cycle. The instruction set of the

TLCS-47 series consists of 1-cycle instructions and 2-cycle

instructions. The former requires 1 cycle for their execution;

the latter, 2 cycles. Each instruction cycle consists of 4 states

(S1 through S4). Each state consists of 2 basic clock pulses.

Figure 2-17. Instruction Cycle

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