F59D1G81MB datasheet(10/54 Pages) ESMT

10 / 54 page

ESMT

F59D1G81MB / F59D1G161MB (2M)

Elite Semiconductor Memory Technology Inc.

Publication Date: Nov.

2018

Revision: 1.1

10/54

Product Introduction

The device is a 1,056Mbit memory organized as 128K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from

column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between

the I/O buffers and memory during page read and page program operations. The program and read operations are executed on a page

basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte

blocks. It indicates that the bit-by-bit erase operation is prohibited on the device.

The device has addresses multiplexed into 8 I/Os or 16I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address

Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle.

For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and

block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory.

Command Set

Function

1st Cycle

2nd Cycle

Acceptable Command

during Busy

Read

00h

30h

Read for Copy-Back

00h

35h

Read ID

90h

Reset

FFh

BLOCK UNLOCK LOW / HIGH

23h

24h

BLOCK LOCK

2Ah

BLOCK LOCK-TIGHT

2Ch

BLOCK LOCK READ STATUS

7Ah

Page Program

80h

10h

Copy-Back Program

85h

10h

Block Erase

60h

D0h

Random Data Input

(1)

85h

Random Data Output

(1)

05h

E0h

Read Status

70h

Cache Program

80h

15h

Cache Read

31h

Read Start for Last Page Cache Read

3Fh

Read Parameter Page

ECh

Read Unique ID

EDh

NOTE: Random Data Input / Output can be executed in a page.

F59D1G81MB Datenblatt(PDF) 10 Page - Elite Semiconductor Memory Technology Inc.

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