LP87702 datasheet(58/98 Pages) TI

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Table 7-31. PGOOD_LEVEL_1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

VMON1_THRESHOLD

R/W

Threshold voltage for VMON1 input:

0x0 – 0.65V (high impedance input, external resistive divider can be

used)

0x1 – 0.80 V

0x2 – 1.00 V

0x3 – 1.10 V

0x4 – 1.20 V

0x5 – 1.30 V

0x6 – 1.80 V

0x7 – 1.80 V

To monitor any other voltage level, select 0x0 and use an external

resistive divider to scale down to 0.65 V. For other than 0x0 VMONx

input is low impedance (internal resistive divider enabled).

(Default from OTP memory)

7.6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h) [reset = 0h]

PGOOD_LEVEL_2 is shown in Figure 7-40 and described in Table 7-32.

Return to Table 7-9.

Figure 7-40. PGOOD_LEVEL_2 Register

VANA_WINDOW

VANA_THRES

HOLD

VMON2_WINDOW

VMON2_THRESHOLD

R/W-0h

Table 7-32. PGOOD_LEVEL_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

VANA_WINDOW

R/W

Overvoltage and undervoltage threshold levels for VANA:

0x0 – ±4%

0x1 – ±5%

0x2 – ±10%

0x3 – ±10%

(Default from OTP memory)

VANA_THRESHOLD

R/W

Threshold voltage for VANA input:

0 – 3.3 V

1 – 5.0 V

(Default from OTP memory)

4-3

VMON2_WINDOW

R/W

Overvoltage and undervoltage threshold levels for VMON2:

0x0 – ±2%

0x1 – ±3%

0x2 – ±4%

0x3 – ±6%

(Default from OTP memory)

2-0

VMON2_THRESHOLD

R/W

Threshold voltage for VMON2 input:

0x0 – 0.65 V (high impedance input, external resistive divider can be

used)

0x1 – 0.80 V

0x2 – 1.00 V

0x3 – 1.10 V

0x4 – 1.20 V

0x5 – 1.30 V

0x6 – 1.80 V

0x7 – 1.80 V

To monitor any other voltage level, select 0x0 and use an external

resistive divider to scale down to 0.65 V. For other than 0x0 VMONx

input is low impedance (internal resistive divider enabled).

(Default from OTP memory)

LP87702

SNVSBU3 – MARCH 2021

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