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SN74HCS02 Datenblatt(PDF) 12 Page - Texas Instruments |
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SN74HCS02 Datenblatt(HTML) 12 Page - Texas Instruments |
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12 / 27 page ![]() 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS02-Q1 to the receiving device(s). 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. 9.2.3 Application Curves R S Q Figure 9-2. Application timing diagram SN74HCS02-Q1 SCLS755C – JULY 2019 – REVISED MARCH 2021 www.ti.com 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS02-Q1 |
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