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WM8569 Datenblatt(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8569 Datenblatt(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 36 page ![]() WM8569 Product Preview w PP Rev 1.1 December 2005 12 MPU INTERFACE TIMING Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT SCLK/IWL rising edge to CSB/IDF rising edge tSCS 60 ns SCLK/IWL pulse cycle time tSCY 80 ns SCLK/IWL pulse width low tSCL 30 ns SCLK/IWL pulse width high tSCH 30 ns SDIN/DM to SCLK/IWL set-up time tDSU 20 ns SCLK/IWL to SDIN/DM hold time tDHO 20 ns CSB/IDF pulse width low tCSL 20 ns CSB/IDF pulse width high tCSH 20 ns CSB/IDF rising to SCLK/IWL rising tCSS 20 ns Table 4 3-Wire SPI Compatible Control Interface Input Timing Information |
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