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WM8569GEDS/RV Datenblatt(PDF) 27 Page - Wolfson Microelectronics plc

Teilenummer WM8569GEDS/RV
Bauteilbeschribung  24-bit, 192kHz Stereo CODEC with Volume Control
PDF  36 Pages
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Hersteller  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8569GEDS/RV Datenblatt(HTML) 27 Page - Wolfson Microelectronics plc

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WM8569
w
PP Rev 1.1 December 2005
27
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8569 generates ADCLRC and ADCBCLK. These clocks are derived from the
master clock and the ratio of ADCMCLK to ADCLRC is set by ADCRATE.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001011
ADCLRC and ADCBCLK
Frequency Select
7:5
ADCRATE [2:0]
010
Master Mode
ADCMCLK:ADCLRC Ratio
Select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the
ADC signal processing oversampling rate to 64fs. The 64fs oversampling rate is only available in
modes were a 96KHz rate is supported, i.e. 256fs or 384fs. In all other modes the ADC will stay in a
128fs oversampling rate irrespective of what this bit is set to.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001011
ADC Oversampling Rate
8
ADCOSR
0
ADC Oversampling Rate Select:
0: 128x oversampling
1: 64x oversampling
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001100
ADC Control
3
ADCHPD
0
ADC Highpass Filter Disable:
0: Highpass filter enabled
1: Highpass filter disabled
In left justified, right justified or I
2S modes, the ADCLRP register bit controls the polarity of ADCLRC.
If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown in Figure
11, Figure 12 and Figure 13. Note that if this feature is used as a means of swapping the left and
right channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register
bit is used to select between modes A and B.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
In Left/Right/I
2S Modes:
ADCLRC Polarity (normal)
0: normal DACLRC polarity
1: inverted DACLRC polarity
0001100
Interface Control
4
ADCLRP
0
In DSP Mode:
0: DSP mode A
1: DSP mode B



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