MX10E8050IPC datasheet(7/88 Pages) MCNIX

7 / 88 page

P/N:PM0887

MX10E8050I /

Specifications subject to change without notice, contact your sales representatives for the most update information.

PRELIMINARY

MX10E8050IA

REV. 1.6, MAR. 28, 2005

FUNCTIONAL DESCRIPTION

General

The MX10E8050I Serial is a stand-alone high-performance and low power microcontroller designed for use in many

applications which need code programmability.

The Flash EPROM offers customers to program the device themselves. This feature increases the flexibility in

many applications, not only in development stage, but also in mass production stage.

In addition to the 80C51 standard functions, the MX10E8050I Serial provides a number of dedicated hardware

functions. MX10E8050I Serial is a control-oriented CPU with on-chip program and data memory. It can execute

program with internal memory up to 64k bytes. MX10E8050I Serial has two software selectable modes of reduced

activity for power reduction Idle, and Power-down. The idle mode freezes the CPU while allowing the RAM, Timers,

serial ports, interrupt system and other peripherals to continue functioning. The Power-down mode saves the RAM

contents but freezes the oscillator causing all other chip functions to be inoperative. Power-down mode can be

terminated by an external reset ,and in addition , by either of the two external interrupts can be terminated as the

power down mode does.

MEMORY ORGANIZATION

The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 256 bytes

internal data memory (RAM), 1k byte auxiliary data memory (AUX-RAM) and 64k byte internal MTP program memory

( FLASH ROM ).

Program Memory

The program memory address space of the MX10E8050I Serial comprises an internal and an external memory

space. The MX10E8050I Serial has 64k byte of program memory on-chip.

Program Protection

If the user choose to set security lock in MTP memory, the program content is protected from reading out of chip.

Internal Data Memory

The internal data memory is divided into three physically separated parts: 256 byte of RAM, 1k bytes of AUX-RAM,

and 128 bytes special function register area (SFR). These parts can be addressed as follows (see Fig.1 and Table. 2)

- RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of

the selected register bank.

- RAM 128 to 255 can only be addressed indirectly . Address pointers are R0 and R1 of the selected register

bank.

- AUX-RAM 0 to 1023 is indirectly addressable as the external data memory locations 0 to 1023 by the

MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. SFRs can only

be addressed directly in the address range from 128 to 255.

MX10E8050IPC Datenblatt(PDF) 7 Page - Macronix International