IC41C82002S datasheet(6/19 Pages) ICSI

6 / 19 page

IC41C82002S

IC41LV82002S

Integrated Circuit Solution Inc.

DR022-0A 08/20/2001

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min.

Max.

Unit

IIL

Input Leakage Current

Any input 0V

≤ VIN ≤ Vcc

–5

µA

Other inputs not under test = 0V

IIO

Output Leakage Current

Output is disabled (Hi-Z)

–5

µA

≤ VOUT ≤ Vcc

VOH

Output High Voltage Level

IOH = –5.0 mA with VCC=5V

2.4

—

IOH = –2.0 mA with VCC=3.3V

VOL

Output Low Voltage Level

IOL = 4.2 mA with VCC=5V

—

0.4

IOL = 2 mA with VCC=3.3V

ICC1

Standby Current: TTL

RAS, CAS

≥ VIH

—

3.3V

—

0.5

ICC2

Standby Current: CMOS

RAS, CAS

≥ VCC – 0.2V

—

3.3V

—

0.5

ICC3

Operating Current:

RAS, CAS,

-50

—

120

Random Read/Write(2,3,4)

Address Cycling, tRC = tRC (min.)

-60

—

110

Average Power Supply Current

ICC4

Operating Current:

RAS = VIL, CAS Cycling,

-50

—

EDO Page Mode(2,3,4)

tRC = tRC (min.)

-60

—

Average Power Supply Current

ICC5

Refresh Current:

RAS Cycling, CAS

≥ VIH

-50

—

120

RAS-Only(2,3)

tRC = tRC (min.)

-60

—

110

Average Power Supply Current

ICC6

Refresh Current:

RAS, CAS Cycling

-50

—

120

CBR(2,3,5)

tRC = tRC (min.)

-60

—

110

Average Power Supply Current

ICCS

Self Refresh Current

Self Refresh Mode

—

300

µA

3.3V

—

300

µA

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

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