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L6981 Datenblatt(PDF) 23 Page - STMicroelectronics |
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L6981 Datenblatt(HTML) 23 Page - STMicroelectronics |
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23 / 49 page ![]() fPLF= 1 2∙π∙RO∙CC (15) fPHF= 1 2∙π∙RO∙CO (16) Whereas the zero is defined as: fZ= 1 2∙π∙RC∙CC (17) 7.3 Voltage divider The contribution of a simple voltage divider is:GDIVs = R2R1+R2 (18) A small signal capacitor in parallel to the upper resistor (only for the adjustable part number) of the voltage divider implements a leading network (fZERO < fPOLE), sometimes necessary to improve the system phase margin: Figure 25. Leading network example (*) Synchronization is allowed for LNM versions only. Laplace transformer of the leading network: GDIVs = R2R1+R2∙ 1+s∙R1∙CR1 1+s∙ R1∙R2 R1+R2∙CR1 (19) fZ= 1 2∙π∙R1∙CR1 (20) fP= 1 2∙π∙ R1∙R2 R1+R2∙CR1 (21) fZ<fP (22) So closing the loop, the loop gain is: Gs =GDIVs ∙GCOs ∙AOs (23) L6981 Voltage divider DS13554 - Rev 1 page 23/49 |
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